DPRG
DPRG List  



DPRG: Optical encoders Help!! Also NMIY0031 does not do interrupts!!

Subject: DPRG: Optical encoders Help!! Also NMIY0031 does not do interrupts!!
From: Kipton Moravec kmoravec at usa.net
Date: Wed Feb 18 10:08:16 CST 1998

Eric B. Olsen wrote:
> Optical encoders are difficult from A to Z.  They're even more difficult to
> use once you get them working! ... since the application level can be quite
> complex!
> 
> For what it's worth, here's some thoughts:
> 
> If I was using Xilinx, I'd never even consider using discrete parts again
> when developing circuits for one!
> 
> In Xilinx, it should be easy to create circuits that can properly decode the
> signals from your encoder.  Also, I use it is to bring out test signals to
> test pins and measure what's going at any point in the circuit ... as I'm
> sure you know.
> 
I will use Xilinx in the final product.  Unfortunately it is not
working.  I do not see glitches in my logic analyzer, and it seems to
work fine in the simulation.  So since it may be something my logic
analyzer is not seeing I decided to see if I got the same results with a
4 bit counter (lS191) and I was getting similar results. 

> As another point, I thinks it's most important to double verify the signal
> format coming from the encoder carefully.  As you know, it's always the
> careful qualification of the input signal that allows success when
> developing an interface.

That is why I looked at it with a scope and logic analyzer. 
Unfortunately the logic analyzer is currently too fast and the signal
goes past so fast on the scope I am not too sure if it is right or not.
That is why I tried the discrete parts.

> 
> Of course, in the final anaysis, the encoder interface circuit should
> support several hardware features, similar to timer modes in a micro, i.e.
> reset functions and capture registers, .... so again, I think Xilinx is the
> best candidate for solving this.
> 
> And so one can see ... I like Xilinx!
>
I am heading out to Tanners to get a LS169, if that works then I know it
is the implimentation of the counter in the Xilinx macro. I need 13
bits.  Anticipating that it will work, I have entered the logic for a
LS169 into a Xilinx macro. (Since Tanners is closed late at night.)

The Xilinx counter like the LS191 did not like the up/down signal to
change when the count enable was enabled. The LS169 only changes on the
rising edge of the clock. The other signals can do whatever they want
until that rising edge.

The HP part Clay sent me to shows they have 4 D Flip-Flops to ensure a
good stable transition.  I can add that to the Xilinx part easily.

The problem in working in VHDL or ABEL is that you do not know exactly
what the part is doing (unless you have a lot more experience than me.)

Regards,
Kip

------------------------------

More information about the DPRG mailing list