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DPRG: Deep Thoughts and rambling

Subject: DPRG: Deep Thoughts and rambling
From: Jim Brown jgbrown at spd.dsccc.com
Date: Fri Jan 9 14:01:10 CST 1998

<snip> 
> I've implemented just this method in my Otto.  Then pulse width
> modulation for the speed control is set up by the CPU but separately
> from the CPU.  I used parallel-serial shift registers driving power FETs
> to energize the motors.  The CPU jams a bit pattern into the register in
> parallel and the register circulates the pattern continuously (clocked
> asynchronously from the CPU at a rate optimized for the motors).  The
> FET is driven by the circulating bit pattern.  The circulating circuit
> contains a gate which can dump the bits and replace them with zeros in
> one circulation, thereby disabling the FET and stopping power to the
> motor.  The limit switches have access to those gates and the CPU polls
> the limit switches.  If a switch is hit the motor stops or at least
> coasts.  Subsequently the CPU responds with a signal to the braking
> relay and decides what else to do next.
<snip>

Very interesting way of doing it.  I've thought of something similar
where if a bumper switch were hit, a relay would flip the motor
power off for an amount of time and would signal the cpu of the 
situation.  When the motor power came back on, the CPU would then decide
a new course of action that wouldn't trip the relay.

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