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[DPRG] tutebot brain breadboard layout question

Subject: [DPRG] tutebot brain breadboard layout question
From: Mike Mccarty Sr jmccarty at ssd.usa.alcatel.com
Date: Thu May 18 11:07:23 CDT 2000

On Thu, 18 May 2000, olio wrote:

> 
> 
> > 
> >                 7400
> >   inputs     +------+
> >              |      |
> >     A   -----|      |------ output
> >              |      |
> >     B   -----|      |
> >              |      |
> >              +------+
> > 
> >              A   B   output
> > 
> >              0   0   0
> >              0   1   0
> >              1   0   0
> >              1   1   1
> 
> thanks for drawing that.  i picked up a few AND and NAND gates while
> out, but i may not have to use them after all since i now have working
> relays.

Unfortunately, the logic table is incorrect. The logic table given is
for an AND gate, while the 7400 is a quad two input NAND gate. The
correct table is (assuming positive logic)

                 7400
   inputs     +------+
              |      |
     A   -----|      |------ output
              |      |
     B   -----|      |
              |      |
              +------+
 
              A   B   output
 
              0   0   1
              0   1   1
              1   0   1
              1   1   0

> i'll keep em around though.
> :^)
> miguel
> 
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