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[DPRG] Re: PWM vs. voltage motor control

Subject: [DPRG] Re: PWM vs. voltage motor control
From: Sluggy slugmusk at linuxlegend.com
Date: Mon Jun 18 13:23:50 CDT 2001

"David P. Anderson" wrote:

> There is a slightly different way of doing PWM that uses constant
> duty cycle with a varying arrangement of "on" and "off" pulses,
> to get around the slew-rate limit problem that Mike describes
> with very narrow pulses/slow motor speeds.

The PWM supplied by the BASIC Stamp may well utilize this algorithm. It
is not simple pulse width, but rather over a specified period of time,
the output will be high for the specified percentage of time.

All this talk of PWM frequency issues prompted me to check the
specifications of the two major ASIC chips that I am familiar with,
specifically the National Semiconductor LM-629 and the Agilent (formerly
Hewlett-Packard) HCTL-1100, to see how their designer approached this

The Agilent documentation specifies that it uses a PWM freqency of 1/100
clk, or 1KHz for the 1MHz part and 2KHz for the 1MHz chip.

The LM-629 is a bit muddier in the specification, but if I understand
correctly, it is 1/512 of clk, or 11718 Hz with a 6MHz clock. 

Obviously, these are widely different approaches.

> The addition of shaft-encoders and some kind of closed loop control,
> like a PID (Proportional Integral Derivitive) controller, can extend
> this range down into the inches-per-day velocities, or as slow as you
> wish.  So the inefficiency of PWM at very narrow pulse widths becomes
> a non-issue.  The speed controller adjusts the pulse dynamically to
> produce a smooth motor response at whatever the requested speed.

Ah, this is what makes the frequency issue go away, to a large degree
anyway, and this is what allows both of the above motion control chips
to be largely interchangable. They both perform closed loop control of
the motion. What frequency they use is of little consequence with their
design goal of speed control.


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