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[DPRG] increased output drive by CMOS and TTL devices

Subject: [DPRG] increased output drive by CMOS and TTL devices
From: R. Bickle rbickle at swbell.net
Date: Wed Jun 27 11:43:12 CDT 2001


Agreed. You can get short rail to rail spikes when paralelling gates.
You caught me on the typos. I was thinking one thing and typing another.

I will summarize for the benefit of the group:

TTL Gates:


CMOS Gates:

4000 Series

CMOS Gates with TTL levels


I'm sure there are some I've missed here, but this should cover most of the
common ones.


-----Original Message-----
>From: Mike McCarty [mailto:jmccarty at ssd.usa.alcatel.com]
Sent: Wednesday, June 27, 2001 11:29 AM
To: R. Bickle
Cc: 'Tom Gralewicz'; dprglist at dprg.org
Subject: RE: [DPRG] increased output drive by CMOS and TTL devices

On Wed, 27 Jun 2001, R. Bickle wrote:

> Tom,
> Most logic families today use CMOS rather than BJT's. With the exception
> LS, AS, and F, all other logic families that come to mind use CMOS. All of
> the newer technologies such as LS, LSTTL, HC, HCT and so forth are CMOS
> devices. Some of these (the T and TTL versions) have adjusted the voltage
> switching threshold in order to behave like TTL devices. (TTL swiches at
> about 1.3 above ground while CMOS switches from 1/3 to 2/3 of VCC.) The
> great advantage of CMOS is higher input impedance, better fanout, and much
> lower power consumption.

You seem to have gotten some confusing typos in there.

LS, AS, F indeed are bipolar. But you repeat them as CMOS. I know you
didn't mean that!

ECL is also bipolar.

> You are right that BJT's in parallel will current hog, but I don't think
> that's the case in most logic gates. I do agree that the best solution to
> the problem is to use a separate driver transistor.

Logic gates won't do that, because they use saturating logic. The
problem mentioned arises when parallelling individual transistors by
simply tying the leads together. One issue I can think of with
parallelling TTL type gates together which does not arise with CMOS is
that TTL has very fast rise and fall, which CMOS does not. This can
result in serious spiking, which would be bad when one gate was trying
to pull all the current, but the other had not yet risen.

Parallelling gates is not a good idea for any logic family.

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