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[DPRG] increased output drive by CMOS and TTL devices

Subject: [DPRG] increased output drive by CMOS and TTL devices
From: Ralph Tenny rten at metronet.com
Date: Wed Jun 27 16:24:56 CDT 2001

Well, I guess my memory has failed me again. (Seems to happen a lot these 

Try this on for size: ECL signals are low amplitude, push-pull (I can't 
remember the word I wanted) signals about 0.2 to 0.4 volt p-p. In this 
mode, with all junctions operating in linear mode, ECL burns power like 
crazy. ECL also requires a level translator to interface the real world.
Did I get that right? So, what is the transition speed of that translator?

The TTL technologies swing (worst-case logic levels) from 0.8v to about 
2.4v, or about 1.6v. Correct?

The HC technology swings essentially rail-to-rail, or 5 volts, typically. 
If you take that into consideration, the HC part is pulling transition 
current about three times as long as 74F (the fastest bipolar). That is 
why board layout is very critical for HC, which I guess is what I was 

NOTE: I keep planning to edit out duplications in DPRG threads and get 
them posted on the website. THIS thread will be a doozy!

On Wed, 27 Jun 2001, Mike McCarty wrote:

> On Wed, 27 Jun 2001, Ralph Tenny wrote:
> > Mike:
> > You said that CMOS does not have fast transition times. The HCCMOS family 
> > has damn fast transitions, faster than any bipolar technology except 
> > (maybe) ECL. Board layout for HC may be more critical than any other 
> > logic family.
> > Ralph
> CMOS (not HCMOS) does not have fast transition times. It depends on
> source voltage, but typically CMOS had rise times 2x that for TTL. See
> http://internt.isk.kth.se/elektro/kursinfo/6B2937_pulsenk/Datablad/National/AN-77.pdf
> HCMOS is comparable to TTL, having 6ns rise and fall times.
> See
> http://www.semiconductors.philips.com/acrobat/various/HCT_FAMILY_SPECIFICATIONS.pdf 
> and
> http://www.dde-eda.com/ecadman/guide/hs.html
>            Family                 Rise time
>                                      ns
>            74LS                      6
>            74F                       2
>            ECL 10K                   1.5
>            ECLips                    0.45
>            GaAs                      0.20
> TTL has rise/fall times intermediate between 74LS and 74F, or on the
> order of 5ns.
> I think that a ratio of 4:1 is a pretty large one. ECL is faster than
> HCMOS to the point that there is really no comparison. There is no
> "maybe" in ECL is faster than HCMOS.
> ECL is not even saturating logic; it is more like very fast OP AMPS,
> and of all the logic families I have dealt with, *the* most difficult
> to use. Any trace over 1 inch requires careful termination. Of course,
> ECL, like TTL, 4000 series CMOS, and 74C CMOS, is pretty much obsolete
> now. (So are 74F and 74ALS for that matter.)
> Note that GaAs is a bipolar techonology. GaAs is 30x as fast as HCMOS.
> I think this qualifies as faster than HCMOS. So HCMOS is not faster
> than any other bipolar technology.
> I certainly would not say that HCMOS might be "more critical than any
> other logic family."
> Apropos of parallelling gates, National specifically supports doing that
> with CMOS gates. See
> http://internt.isk.kth.se/elektro/kursinfo/6B2937_pulsenk/Datablad/National/AN-77.pdf
> This is, of course, for the old 4000 and 74C series, not the B series
> or HC(T).
> Here are some interesting pages I came across
> http://ugweb.cs.ualberta.ca/~c280/manual/section3_1.html
> http://www.ece.drexel.edu/ECE/ECE-L301/LSTTL_list.pdf
> http://www.dde-eda.com/ecadman/guide/hs.html
> Mike
> -- 
> char *p="char *p=%c%s%c;main(){printf(p,34,p,34);}";main(){printf(p,34,p,34);}
> This message made from 100% recycled bits.
> I can explain it for you, but I can't understand it for you.
> I don't speak for Alcatel      <- They make me say that.

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