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[DPRG] voltage multiplier for NMOS Hbridge

Subject: [DPRG] voltage multiplier for NMOS Hbridge
From: Ted Huntington thunting at uci.edu
Date: Fri Jun 27 15:33:01 CDT 2003

Thanks for taking the time to draw those circuit diagrams Chuck.  I am really a
novice at this even though I graduated in computer engineering we never did basic
electronics and should have.

That problem with the 24V voltage drop is something I wasn't aware of.  Now I see
that I was using 24V Vgs on the low side nmos transistors (for the 2 pnp 2 npn
h-bridge), I should have probably used 12V.  Also I see that the high side nmos
would have to have a low 4 to 24 volts (for a 24 V source).

I see that the high side of a 4 nmos h-bridge moves current (I guess electrons
actually move from ground to +24) from drain to source (that is not really
intuitive to me).  That is pretty confusing that the drain has 24V and the Vgs is
????  I guess the Vs on the high side motor starts at 0 (or high impedence) and is
turned on because of a Vgs=24V (or whatever I suppose this should be <20V).  Then
as the motor voltage at the source gets the 24V from the drain I guess Vgs would be
less?

I decided to buy some HIP4081A chips to test $5 at newark.com.   I found the link:
 http://www.solutions-cubed.com/Stamp/sep99.pdf
that has a sample circuit.

Now the questions I have are:
1) Use a 12V regular to lower the 24V on all 20 h-bridges or
2) Wire 12V from 1 of 2 12V batteries to each of the 20 h-bridges

the HIP4081A does have shoot-thru protection (as far as I have deciphered) but some
capacitors and diodes are needed (although how many and what values are not clear).

I am still confused about how the HIP4081A boost voltage and high side connector
works.  The high side voltage connects to the high side MOSFET source (and the
motor), how does the HIP4081A Vgs maintain 10V higher than the changing Vsource?  I
guess I will find out!

bot until the botting's thru,
Ted

>
> < 1V!) and if your Gate voltage was 10V relative to the battery, as the
> lamp begins to conduct current, the voltage drop across the lamp goes up,
> and the measured voltage between Gate and Source goes *down*! What happens
> in reality is that the system settles on a voltage where the decrease in
> gate voltage is exactly enough to set the FET to carry the lamps current.
> Since the FET is not fully enhanced any more it begins to dissipate heat at
> the rate of current * the voltage drop across the FET.
>
> A final change to the circuit fixes this problem like so:
>
>                 +------------------+
>                 |                  |
>               Drain             Positive
>                 |                  |
>              +--+--+          +----+----+
>              |     |          | BATTERY |
>      +-Gate -+ FET |          +----+----+
>      |       |     |               |
>     Pos      +--+--+             Negative
>      |          |                  |
> +---+----+   Source               |
> |10V Batt|     |                  |
> +---+----+     |                  |
>      |          |                  |
>     Neg         |                  |
>      |          |      +------+    |
>      +----------+------+ LAMP +----+
>                        +------+
>
> Now there is a *separate* supply to turn on the FET, this supply is
> connected so that its "ground" is attached to the source, and its output is
> attached to the gate. This way if the Source pin of the FET gets "pushed
> up" relative to the batteries voltage then that also pushes up where the
> ground level is on the Gate's battery and so the gate "sees" a constant 10V
> which keeps the FET on all the time.
>
> The interesting bit, is that in an H-bridge this gate voltage will be 10 to
> 15 volts higher than the battery voltage when the FET is on, so you can't
> derive it easily from the battery voltage. (its tricky to make voltages go
> "up" as you have discovered).
>
> The bottom line is that for most FETs a voltage of 15V, when measured
> between gate and source, will turn them fully "on." This voltage is
> independent of the voltage being applied to the Drain, or the voltage that
> appears on the Source. If the voltage on the source can change depending on
> how much current the FET is conducting, then you must isolate the voltage
> to the gate from those changes.
>

--
Ted Huntington
Programmer Analyst I
Main Library
University of California, Irvine
PO Box 19557
Irvine, CA 92623-9557

Phone Bus Off 949 824 8926
Phone MRC     949 824 1674
emesg: thunting at uci.edu
webpage:  http://business.lib.uci.edu/webpages/ted.htm
"Stop violence, teach science."



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