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[DPRG] serial to parallel shift register with_individually_tristate outputs

Subject: [DPRG] serial to parallel shift register with_individually_tristate outputs
From: Randy M. Dumse rmd at newmicros.com
Date: Tue Oct 11 08:56:40 CDT 2011

Paul Bouchier said: Monday, October 10, 2011 10:33 PM
> If speed is an issue for you, you might consider a CPLD 
> (Complex PLD) 

My thoughts as well. I downloaded the Xilinx development system
and bought the development kit after the Nu Horizon's guy came
out and presented to DPRG a number of years back. Really got me
excited about the Cool Runner II. Had big ideas and big plans,
but never had enough time to get into it. 

But yes, I think this could be a very interesting simple
project. Think you can put TTL packages into their design
package, and then compile to code, so this would be like having
two '595's and a tristate buffer. I don't remember the number,
but there's an individually enabled buffer. Maybe a '125? Yes,
that's it. http://www.ti.com/product/sn74hc125 A Quadruple Bus
Buffer Gates with 3-State Output. So you use one '595 to receive
data, the other to receive enabling for the buffers, and then
two '125's to buffer.

PLDs of most ilk are getting very hard to come by. We used low
power ones, and we're paying as much as $20 a piece to get them,
when we can find them. We can't afford to sell some boards
anymore, so I personally am anxious to learn the CPLD's as
replacements.

Randy


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